ss_spi.c: fix CTRLR0 write in ss_spi_set_data_mode()

This fixes two existing issues with the current implementation;
  1. The value to be written (ctrl) is completely overwritten on line 107,
     erasing the previous modifications (perhaps instead of a bitwise-OR?)
  2. On the same line- the 'dataMode' value should be shifted by 4, not by 6
     (see Quark SE C1000 datasheet, Table 229 "Detailed Description of
      Control Register 0 (CTRLR0) for reference)

Author: eriknyquist

system/libarc32_arduino101/drivers/spi_priv.h

@@ -60,8 +60,8 @@
 #define     SPI_NDF_SET_MASK    (0x0000ffff)
 #define     SPI_SRL_SET_MASK    (0xfffff7ff)
 #define     SPI_TMOD_SET_MASK   (0xfffffcff)
-#define     SPI_SCPL_SET_MASK   (0xffffff7f)
-#define     SPI_SCPH_SET_MASK   (0xffffffbf)
+#define     SPI_SCPL_SET_MASK   (0x80)
+#define     SPI_SCPH_SET_MASK   (0x40)
 #define     SPI_DFS_SET_MASK    (0xfffffff0)
 
 #define     SPI_CLK_ENABLED     (1 << 15)

system/libarc32_arduino101/drivers/ss_spi.c

@@ -103,8 +103,8 @@ void ss_spi_set_data_mode(SPI_CONTROLLER controller_id, uint8_t dataMode)
 
     /* Set frame size, bus mode and transfer mode */
     ctrl = READ_ARC_REG(dev->reg_base + CTRL);
-    ctrl &= (SPI_SCPL_SET_MASK & SPI_SCPH_SET_MASK);
-    ctrl = (dataMode << 6);
+    ctrl |= (SPI_SCPL_SET_MASK | SPI_SCPH_SET_MASK);
+    ctrl |= (dataMode & 0xFC) << 4;
     WRITE_ARC_REG(ctrl, dev->reg_base + CTRL);
 
     /* re-enable controller */