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10 | 10 |
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11 | 11 | //////////////////////////////////////////////////////////////////////////
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12 | 12 | // //
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13 |
| -// Implementation of HAL that builds on top of aocl_mmd (board vendor // |
| 13 | +// Versioning constants, address maps, and bit/byte positionings used // |
| 14 | +// in acl_kernel_if and acl_pll // |
| 15 | +// // |
| 16 | +////////////////////////////////////////////////////////////////////////// |
| 17 | + |
| 18 | +//// acl_kernel_if |
| 19 | +// Versioning: This value must be read from addr 0 |
| 20 | +// For unit tests to work, this defines must match the one in the unit test |
| 21 | +// header file |
| 22 | +#define KERNEL_VERSION_ID (0xa0c00001) |
| 23 | +#define KERNEL_ROM_VERSION_ID (0xa0c00002) |
| 24 | +// Version number in the top 16-bits of the 32-bit status register. Used |
| 25 | +// to verify that the hardware and HAL have an identical view of the CSR |
| 26 | +// address map. |
| 27 | +#define CSR_VERSION_ID_18_1 (3) |
| 28 | +#define CSR_VERSION_ID_19_1 (4) |
| 29 | +#define CSR_VERSION_ID_23_1 (5) |
| 30 | +#define CSR_VERSION_ID CSR_VERSION_ID_23_1 |
| 31 | + |
| 32 | +// Address map |
| 33 | +// For unit tests to work, these defines must match those in the unit test |
| 34 | +// header file |
| 35 | +#define OFFSET_KERNEL_VERSION_ID ((dev_addr_t)0x0000) |
| 36 | +#define OFFSET_KERNEL_CRA_SEGMENT ((dev_addr_t)0x0020) |
| 37 | +#define OFFSET_SW_RESET ((dev_addr_t)0x0030) |
| 38 | +#define OFFSET_KERNEL_CRA ((dev_addr_t)0x1000) |
| 39 | +#define OFFSET_CONFIGURATION_ROM ((dev_addr_t)0x2000) |
| 40 | + |
| 41 | +// Addressses for Kernel System ROM |
| 42 | +#define OFFSET_KERNEL_ROM_LOCATION_MSB (0x3ffffff8) |
| 43 | +#define OFFSET_KERNEL_ROM_LOCATION_LSB (0x3ffffffc) |
| 44 | +#define OFFSET_KERNEL_MAX_ADDRESS (0x3fffffff) |
| 45 | + |
| 46 | +#define KERNEL_CRA_SEGMENT_SIZE (0x1000) |
| 47 | +#define KERNEL_ROM_SIZE_BYTES_READ 4 |
| 48 | +#define KERNEL_ROM_SIZE_BYTES 8 |
| 49 | + |
| 50 | +// Byte offsets into the CRA: |
| 51 | +// For CSR version >= 5 byte offsets are pushed back with the proper |
| 52 | +// value except for the CSR later on in the runtime execution |
| 53 | +#define KERNEL_OFFSET_CSR 0 |
| 54 | +#define KERNEL_OFFSET_PRINTF_BUFFER_SIZE 0x4 |
| 55 | +#define KERNEL_OFFSET_CSR_PROFILE_CTRL 0xC |
| 56 | +#define KERNEL_OFFSET_CSR_PROFILE_DATA 0x10 |
| 57 | +#define KERNEL_OFFSET_CSR_PROFILE_START_CYCLE 0x18 |
| 58 | +#define KERNEL_OFFSET_CSR_PROFILE_STOP_CYCLE 0x20 |
| 59 | +#define KERNEL_OFFSET_FINISH_COUNTER 0x28 |
| 60 | +#define KERNEL_OFFSET_INVOCATION_IMAGE 0x30 |
| 61 | + |
| 62 | +// CSR version >= 5 byte offsets |
| 63 | +#define KERNEL_OFFSET_START_REG 0x8 |
| 64 | + |
| 65 | +// Backwards compatibility with CSR_VERSION_ID 3 |
| 66 | +#define KERNEL_OFFSET_INVOCATION_IMAGE_181 0x28 |
| 67 | + |
| 68 | +// Bit positions |
| 69 | +#define KERNEL_CSR_START 0 |
| 70 | +#define KERNEL_CSR_DONE 1 |
| 71 | +#define KERNEL_CSR_STALLED 3 |
| 72 | +#define KERNEL_CSR_UNSTALL 4 |
| 73 | +#define KERNEL_CSR_PROFILE_TEMPORAL_STATUS 5 |
| 74 | +#define KERNEL_CSR_PROFILE_TEMPORAL_RESET 6 |
| 75 | +#define KERNEL_CSR_LAST_STATUS_BIT KERNEL_CSR_PROFILE_TEMPORAL_RESET |
| 76 | +#define KERNEL_CSR_STATUS_BITS_MASK \ |
| 77 | + ((unsigned)((1 << (KERNEL_CSR_LAST_STATUS_BIT + 1)) - 1)) |
| 78 | +#define KERNEL_CSR_LMEM_INVALID_BANK 11 |
| 79 | +#define KERNEL_CSR_LSU_ACTIVE 12 |
| 80 | +#define KERNEL_CSR_WR_ACTIVE 13 |
| 81 | +#define KERNEL_CSR_BUSY 14 |
| 82 | +#define KERNEL_CSR_RUNNING 15 |
| 83 | +#define KERNEL_CSR_FIRST_VERSION_BIT 16 |
| 84 | +#define KERNEL_CSR_LAST_VERSION_BIT 31 |
| 85 | + |
| 86 | +#define KERNEL_CSR_PROFILE_SHIFT64_BIT 0 |
| 87 | +#define KERNEL_CSR_PROFILE_RESET_BIT 1 |
| 88 | +#define KERNEL_CSR_PROFILE_ALLOW_PROFILING_BIT 2 |
| 89 | +#define KERNEL_CSR_PROFILE_LOAD_BUFFER_BIT 3 |
| 90 | +#define KERNEL_CSR_PROFILE_SHARED_CONTROL_BIT1 4 |
| 91 | +#define KERNEL_CSR_PROFILE_SHARED_CONTROL_BIT2 5 |
| 92 | + |
| 93 | +#define CONFIGURATION_ROM_BYTES 4096 |
| 94 | + |
| 95 | +#define RESET_TIMEOUT (2 * 1000 * 1000 * 1000) |
| 96 | + |
| 97 | +//// acl_pll |
| 98 | +// Address map |
| 99 | +// For unit tests to work, these defines must match those in the unit test |
| 100 | +// header file |
| 101 | +#define OFFSET_PLL_VERSION_ID ((dev_addr_t)0x000) |
| 102 | +#define OFFSET_ROM ((dev_addr_t)0x400) |
| 103 | +#define OFFSET_RECONFIG_CTRL ((dev_addr_t)0x200) |
| 104 | +#define OFFSET_RECONFIG_CTRL_20NM ((dev_addr_t)0x800) |
| 105 | +#define OFFSET_COUNTER ((dev_addr_t)0x100) |
| 106 | +#define OFFSET_RESET ((dev_addr_t)0x110) |
| 107 | +#define OFFSET_LOCK ((dev_addr_t)0x120) |
| 108 | + |
| 109 | +// Constants |
| 110 | +#define MAX_KNOWN_SETTINGS 100 |
| 111 | +#define MAX_POSSIBLE_FMAX 2000000 |
| 112 | +#define MAX_RECONFIG_RETRIES 3 |
| 113 | +#define RECONFIG_TIMEOUT (1000000000ll) |
| 114 | +#define CLK_MEASUREMENT_PERIOD (16 * 1024 * 1024) |
| 115 | + |
| 116 | +////////////////////////////////////////////////////////////////////////// |
| 117 | +// // |
| 118 | +// Implementation of HAL that builds on top of aocl_mmd (board vendor // |
14 | 119 | // visible), acl_pll, and acl_kernel_if. //
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15 | 120 | // //
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16 | 121 | //////////////////////////////////////////////////////////////////////////
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