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[WIP] [CodeGen] Enable TrapUnreachable by default for all targets.
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-397
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105 files changed

+584
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lines changed

‎llvm/include/llvm/Target/TargetOptions.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -145,7 +145,7 @@ namespace llvm {
145145
DataSections(false), IgnoreXCOFFVisibility(false),
146146
XCOFFTracebackTable(true), UniqueSectionNames(true),
147147
UniqueBasicBlockSectionNames(false), SeparateNamedSections(false),
148-
TrapUnreachable(false), NoTrapAfterNoreturn(false), TLSSize(0),
148+
TrapUnreachable(true), NoTrapAfterNoreturn(true), TLSSize(0),
149149
EmulatedTLS(false), EnableTLSDESC(false), EnableIPRA(false),
150150
EmitStackSizeSection(false), EnableMachineOutliner(false),
151151
EnableMachineFunctionSplitter(false), SupportsDefaultOutlining(false),

‎llvm/lib/CodeGen/LLVMTargetMachine.cpp

Lines changed: 13 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -33,11 +33,11 @@
3333
#include "llvm/Target/TargetOptions.h"
3434
using namespace llvm;
3535

36-
static cl::opt<bool>
37-
EnableTrapUnreachable("trap-unreachable", cl::Hidden,
38-
cl::desc("Enable generating trap for unreachable"));
36+
cl::opt<bool> EnableTrapUnreachable(
37+
"trap-unreachable", cl::Hidden,
38+
cl::desc("Enable generating trap for unreachable"));
3939

40-
static cl::opt<bool> EnableNoTrapAfterNoreturn(
40+
cl::opt<bool> EnableNoTrapAfterNoreturn(
4141
"no-trap-after-noreturn", cl::Hidden,
4242
cl::desc("Do not emit a trap instruction for 'unreachable' IR instructions "
4343
"after noreturn calls, even if --trap-unreachable is set."));
@@ -96,10 +96,15 @@ LLVMTargetMachine::LLVMTargetMachine(const Target &T,
9696
this->CMModel = CM;
9797
this->OptLevel = OL;
9898

99-
if (EnableTrapUnreachable)
100-
this->Options.TrapUnreachable = true;
101-
if (EnableNoTrapAfterNoreturn)
102-
this->Options.NoTrapAfterNoreturn = true;
99+
if (EnableTrapUnreachable.getNumOccurrences())
100+
this->Options.TrapUnreachable = EnableTrapUnreachable;
101+
102+
if (EnableNoTrapAfterNoreturn.getNumOccurrences())
103+
this->Options.NoTrapAfterNoreturn = EnableNoTrapAfterNoreturn;
104+
105+
// Keep all traps in debug environments.
106+
else if (OL == CodeGenOptLevel::None)
107+
this->Options.NoTrapAfterNoreturn = false;
103108
}
104109

105110
TargetTransformInfo

‎llvm/lib/Target/AArch64/AArch64TargetMachine.cpp

Lines changed: 1 addition & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -360,11 +360,6 @@ AArch64TargetMachine::AArch64TargetMachine(const Target &T, const Triple &TT,
360360
TLOF(createTLOF(getTargetTriple())), isLittle(LittleEndian) {
361361
initAsmInfo();
362362

363-
if (TT.isOSBinFormatMachO()) {
364-
this->Options.TrapUnreachable = true;
365-
this->Options.NoTrapAfterNoreturn = true;
366-
}
367-
368363
if (getMCAsmInfo()->usesWindowsCFI()) {
369364
// Unwinding can get confused if the last instruction in an
370365
// exception-handling region (function, funclet, try block, etc.)
@@ -373,6 +368,7 @@ AArch64TargetMachine::AArch64TargetMachine(const Target &T, const Triple &TT,
373368
// FIXME: We could elide the trap if the next instruction would be in
374369
// the same region anyway.
375370
this->Options.TrapUnreachable = true;
371+
this->Options.NoTrapAfterNoreturn = false;
376372
}
377373

378374
if (this->Options.TLSSize == 0) // default

‎llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -396,6 +396,8 @@ static cl::opt<bool>
396396
cl::desc("Enable AMDGPUAttributorPass"),
397397
cl::init(true), cl::Hidden);
398398

399+
extern cl::opt<bool> EnableTrapUnreachable;
400+
399401
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
400402
// Register the target
401403
RegisterTargetMachine<R600TargetMachine> X(getTheR600Target());
@@ -612,6 +614,10 @@ AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
612614
FS, Options, getEffectiveRelocModel(RM),
613615
getEffectiveCodeModel(CM, CodeModel::Small), OptLevel),
614616
TLOF(createTLOF(getTargetTriple())) {
617+
// FIXME: There are some scenarios where targets may not have hardware traps,
618+
// and external calls to `abort` also fail. For now, do a blanket-disable.
619+
if (!EnableTrapUnreachable.getNumOccurrences())
620+
this->Options.TrapUnreachable = false;
615621
initAsmInfo();
616622
if (TT.getArch() == Triple::amdgcn) {
617623
if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize64"))

‎llvm/lib/Target/ARM/ARMTargetMachine.cpp

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -251,11 +251,6 @@ ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const Triple &TT,
251251
this->Options.EABIVersion = EABI::EABI5;
252252
}
253253

254-
if (TT.isOSBinFormatMachO()) {
255-
this->Options.TrapUnreachable = true;
256-
this->Options.NoTrapAfterNoreturn = true;
257-
}
258-
259254
// ARM supports the debug entry values.
260255
setSupportsDebugEntryValues(true);
261256

‎llvm/lib/Target/BPF/BPFTargetMachine.cpp

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -34,6 +34,8 @@
3434
#include <optional>
3535
using namespace llvm;
3636

37+
extern cl::opt<bool> EnableTrapUnreachable;
38+
3739
static cl::
3840
opt<bool> DisableMIPeephole("disable-bpf-peephole", cl::Hidden,
3941
cl::desc("Disable machine peepholes for BPF"));
@@ -74,6 +76,12 @@ BPFTargetMachine::BPFTargetMachine(const Target &T, const Triple &TT,
7476
getEffectiveCodeModel(CM, CodeModel::Small), OL),
7577
TLOF(std::make_unique<TargetLoweringObjectFileELF>()),
7678
Subtarget(TT, std::string(CPU), std::string(FS), *this) {
79+
// FIXME: If the user has not explicitly enabled TrapUnreachable,
80+
// disable it. We do not have an explicit trap opcode and external calls
81+
// to abort are a no-no.
82+
if (!EnableTrapUnreachable.getNumOccurrences())
83+
this->Options.TrapUnreachable = false;
84+
7785
initAsmInfo();
7886

7987
BPFMCAsmInfo *MAI =

‎llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -146,6 +146,8 @@ static cl::opt<bool> EnableInstSimplify("hexagon-instsimplify", cl::Hidden,
146146
cl::init(true),
147147
cl::desc("Enable instsimplify"));
148148

149+
extern cl::opt<bool> EnableTrapUnreachable;
150+
149151
/// HexagonTargetMachineModule - Note that this is used on hosts that
150152
/// cannot link in a library unless there are references into the
151153
/// library. In particular, it seems that it is not possible to get
@@ -284,6 +286,11 @@ HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
284286
(HexagonNoOpt ? CodeGenOptLevel::None : OL)),
285287
TLOF(std::make_unique<HexagonTargetObjectFile>()),
286288
Subtarget(Triple(TT), CPU, FS, *this) {
289+
// FIXME: If the user has not explicitly enabled TrapUnreachable,
290+
// disable it. We currently seem to have problems with EH_RETURN lowering.
291+
if (!EnableTrapUnreachable.getNumOccurrences())
292+
this->Options.TrapUnreachable = false;
293+
287294
initializeHexagonCopyHoistingPass(*PassRegistry::getPassRegistry());
288295
initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry());
289296
initializeHexagonLoopAlignPass(*PassRegistry::getPassRegistry());

‎llvm/lib/Target/X86/X86TargetMachine.cpp

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -242,10 +242,11 @@ X86TargetMachine::X86TargetMachine(const Target &T, const Triple &TT,
242242
OL),
243243
TLOF(createTLOF(getTargetTriple())), IsJIT(JIT) {
244244
// On PS4/PS5, the "return address" of a 'noreturn' call must still be within
245-
// the calling function, and TrapUnreachable is an easy way to get that.
246-
if (TT.isPS() || TT.isOSBinFormatMachO()) {
245+
// the calling function, and unsetting NoTrapAfterNoreturn
246+
// is an easy way to get that.
247+
if (TT.isPS()) {
247248
this->Options.TrapUnreachable = true;
248-
this->Options.NoTrapAfterNoreturn = TT.isOSBinFormatMachO();
249+
this->Options.NoTrapAfterNoreturn = false;
249250
}
250251

251252
setMachineOutliner(true);

‎llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -137,6 +137,8 @@ define i32 @test_cfg_remap_multiple_preds(i32 %in) {
137137
; CHECK-NEXT: bb.2.odd:
138138
; CHECK-NEXT: successors:
139139
; CHECK-NEXT: {{ $}}
140+
; CHECK-NEXT: G_TRAP
141+
; CHECK-NEXT: {{ $}}
140142
; CHECK-NEXT: bb.3.next:
141143
; CHECK-NEXT: G_BR %bb.5
142144
; CHECK-NEXT: {{ $}}
@@ -1147,18 +1149,28 @@ define void @jt_2_tables_phi_edge_from_second() {
11471149
; CHECK-NEXT: bb.2.if.then:
11481150
; CHECK-NEXT: successors:
11491151
; CHECK-NEXT: {{ $}}
1152+
; CHECK-NEXT: G_TRAP
1153+
; CHECK-NEXT: {{ $}}
11501154
; CHECK-NEXT: bb.3.sw.bb2.i41:
11511155
; CHECK-NEXT: successors:
11521156
; CHECK-NEXT: {{ $}}
1157+
; CHECK-NEXT: G_TRAP
1158+
; CHECK-NEXT: {{ $}}
11531159
; CHECK-NEXT: bb.4.sw.bb7.i44:
11541160
; CHECK-NEXT: successors:
11551161
; CHECK-NEXT: {{ $}}
1162+
; CHECK-NEXT: G_TRAP
1163+
; CHECK-NEXT: {{ $}}
11561164
; CHECK-NEXT: bb.5.sw.bb8.i45:
11571165
; CHECK-NEXT: successors:
11581166
; CHECK-NEXT: {{ $}}
1167+
; CHECK-NEXT: G_TRAP
1168+
; CHECK-NEXT: {{ $}}
11591169
; CHECK-NEXT: bb.6.sw.bb13.i47:
11601170
; CHECK-NEXT: successors:
11611171
; CHECK-NEXT: {{ $}}
1172+
; CHECK-NEXT: G_TRAP
1173+
; CHECK-NEXT: {{ $}}
11621174
; CHECK-NEXT: bb.7.sw.bb14.i48:
11631175
; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[DEF1]](s32), [[C5]]
11641176
; CHECK-NEXT: G_BRCOND [[ICMP5]](s1), %bb.10
@@ -1202,6 +1214,8 @@ define void @jt_2_tables_phi_edge_from_second() {
12021214
; CHECK-NEXT: bb.8.sw.default.i49:
12031215
; CHECK-NEXT: successors:
12041216
; CHECK-NEXT: {{ $}}
1217+
; CHECK-NEXT: G_TRAP
1218+
; CHECK-NEXT: {{ $}}
12051219
; CHECK-NEXT: bb.9.sw.bb1.i:
12061220
; CHECK-NEXT: G_BR %bb.16
12071221
; CHECK-NEXT: {{ $}}
@@ -1234,6 +1248,7 @@ define void @jt_2_tables_phi_edge_from_second() {
12341248
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
12351249
; CHECK-NEXT: BL @jt_2_tables_phi_edge_from_second, csr_aarch64_aapcs, implicit-def $lr, implicit $sp
12361250
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
1251+
; CHECK-NEXT: G_TRAP
12371252
; CHECK-NEXT: {{ $}}
12381253
; CHECK-NEXT: bb.18.while.end:
12391254
; CHECK-NEXT: [[PHI1:%[0-9]+]]:_(s32) = G_PHI [[C21]](s32), %bb.30, [[PHI]](s32), %bb.16
@@ -1460,6 +1475,7 @@ define i1 @i1_value_cmp_is_signed(i1) {
14601475
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
14611476
; CHECK-NEXT: BL @bar, csr_aarch64_aapcs, implicit-def $lr, implicit $sp
14621477
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
1478+
; CHECK-NEXT: G_TRAP
14631479
; CHECK-NEXT: {{ $}}
14641480
; CHECK-NEXT: bb.3.OkValue:
14651481
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s8) = G_ZEXT [[TRUNC1]](s1)

‎llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -431,8 +431,7 @@ end:
431431

432432
; CHECK-LABEL: name: unreachable
433433
; CHECK: G_ADD
434-
; CHECK-NEXT: {{^$}}
435-
; CHECK-NEXT: ...
434+
; CHECK-NEXT: G_TRAP
436435
define void @unreachable(i32 %a) {
437436
%sum = add i32 %a, %a
438437
unreachable

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