Skip to content

Commit fd33eac

Browse files
guoxin049guoxin049
committed
fix issues 108019
1 parent 0a17bdf commit fd33eac

29 files changed

+233
-244
lines changed

‎clang/docs/ReleaseNotes.rst

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -548,6 +548,11 @@ Miscellaneous Clang Crashes Fixed
548548
- Fixed internal assertion firing when a declaration in the implicit global
549549
module is found through ADL. (GH#109879)
550550

551+
Leaf Functions Do Not Retain FP Bug Fixed
552+
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
553+
554+
- Fixed ``-fno-omit-frame-pointer`` leaf functions do not retain fp.(#GH108019)
555+
551556
OpenACC Specific Changes
552557
------------------------
553558

‎llvm/docs/ReleaseNotes.md

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -125,6 +125,11 @@ Changes to the ARM Backend
125125
the required alignment space with a sequence of `0x0` bytes (the requested
126126
fill value) rather than NOPs.
127127

128+
* The default behavior for frame pointers in leaf functions has been updated. When
129+
`-fno-omit-frame-pointer` is specified, the frame pointer (FP) will now be retained
130+
in leaf functions by default. To eliminate the frame pointer in leaf functions, the
131+
`-momit-leaf-frame-pointer` option must be explicitly provided.
132+
128133
Changes to the AVR Backend
129134
--------------------------
130135

‎llvm/include/llvm/CodeGen/TargetFrameLowering.h

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -277,12 +277,6 @@ class TargetFrameLowering {
277277
return false;
278278
}
279279

280-
/// Return true if the target wants to keep the frame pointer regardless of
281-
/// the function attribute "frame-pointer".
282-
virtual bool keepFramePointer(const MachineFunction &MF) const {
283-
return false;
284-
}
285-
286280
/// hasFP - Return true if the specified function should have a dedicated
287281
/// frame pointer register. For most targets this is true only if the function
288282
/// has variable sized allocas or if frame pointer elimination is disabled.

‎llvm/lib/CodeGen/TargetOptionsImpl.cpp

Lines changed: 0 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -22,10 +22,6 @@ using namespace llvm;
2222
/// DisableFramePointerElim - This returns true if frame pointer elimination
2323
/// optimization should be disabled for the given machine function.
2424
bool TargetOptions::DisableFramePointerElim(const MachineFunction &MF) const {
25-
// Check to see if the target want to forcibly keep frame pointer.
26-
if (MF.getSubtarget().getFrameLowering()->keepFramePointer(MF))
27-
return true;
28-
2925
const Function &F = MF.getFunction();
3026

3127
if (!F.hasFnAttribute("frame-pointer"))
@@ -41,10 +37,6 @@ bool TargetOptions::DisableFramePointerElim(const MachineFunction &MF) const {
4137
}
4238

4339
bool TargetOptions::FramePointerIsReserved(const MachineFunction &MF) const {
44-
// Check to see if the target want to forcibly keep frame pointer.
45-
if (MF.getSubtarget().getFrameLowering()->keepFramePointer(MF))
46-
return true;
47-
4840
const Function &F = MF.getFunction();
4941

5042
if (!F.hasFnAttribute("frame-pointer"))

‎llvm/lib/Target/ARM/ARMFrameLowering.cpp

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -324,6 +324,10 @@ bool ARMFrameLowering::hasFP(const MachineFunction &MF) const {
324324
const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
325325
const MachineFrameInfo &MFI = MF.getFrameInfo();
326326

327+
// Check to see if the target want to forcibly keep frame pointer.
328+
if (keepFramePointer(MF))
329+
return true;
330+
327331
// ABI-required frame pointer.
328332
if (MF.getTarget().Options.DisableFramePointerElim(MF))
329333
return true;
@@ -2365,7 +2369,8 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF,
23652369
// to take advantage the eliminateFrameIndex machinery. This also ensures it
23662370
// is spilled in the order specified by getCalleeSavedRegs() to make it easier
23672371
// to combine multiple loads / stores.
2368-
bool CanEliminateFrame = !(requiresAAPCSFrameRecord(MF) && hasFP(MF));
2372+
bool CanEliminateFrame = !(requiresAAPCSFrameRecord(MF) && hasFP(MF)) &&
2373+
!MF.getTarget().Options.DisableFramePointerElim(MF);
23692374
bool CS1Spilled = false;
23702375
bool LRSpilled = false;
23712376
unsigned NumGPRSpills = 0;

‎llvm/lib/Target/ARM/ARMFrameLowering.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -41,7 +41,7 @@ class ARMFrameLowering : public TargetFrameLowering {
4141
MutableArrayRef<CalleeSavedInfo> CSI,
4242
const TargetRegisterInfo *TRI) const override;
4343

44-
bool keepFramePointer(const MachineFunction &MF) const override;
44+
bool keepFramePointer(const MachineFunction &MF) const;
4545

4646
bool enableCalleeSaveSkip(const MachineFunction &MF) const override;
4747

‎llvm/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@
99

1010
@oStruct = external global %struct.Outer, align 4
1111

12-
define void @main(i8 %val8) nounwind {
12+
define void @main(i8 %val8) nounwind "frame-pointer"="none" {
1313
; CHECK-LABEL: main:
1414
; CHECK: @ %bb.0: @ %for.body.lr.ph
1515
; CHECK-NEXT: movw r0, :lower16:(L_oStruct$non_lazy_ptr-(LPC0_0+4))

‎llvm/test/CodeGen/ARM/2011-12-19-sjlj-clobber.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
; Radar 10567930: Make sure that all the caller-saved registers are saved and
44
; restored in a function with setjmp/longjmp EH. In particular, r6 was not
55
; being saved here.
6-
; CHECK: push {r4, r5, r6, r7, lr}
6+
; CHECK: push.w {r4, r5, r6, r7, r8, r10, r11, lr}
77

88
%0 = type opaque
99
%struct.NSConstantString = type { ptr, i32, ptr, i32 }

‎llvm/test/CodeGen/ARM/arm-shrink-wrapping.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1732,7 +1732,7 @@ if.end:
17321732
; Another infinite loop test this time with two nested infinite loop.
17331733
; infiniteloop3
17341734
; bx lr
1735-
define void @infiniteloop3() "frame-pointer"="all" {
1735+
define void @infiniteloop3() "frame-pointer"="none" {
17361736
; ARM-LABEL: infiniteloop3:
17371737
; ARM: @ %bb.0: @ %entry
17381738
; ARM-NEXT: mov r0, #0

‎llvm/test/CodeGen/ARM/atomic-load-store.ll

Lines changed: 26 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -324,18 +324,17 @@ define void @test_old_store_64bit(ptr %p, i64 %v) {
324324
;
325325
; ARMOPTNONE-LABEL: test_old_store_64bit:
326326
; ARMOPTNONE: @ %bb.0:
327-
; ARMOPTNONE-NEXT: push {r4, r5, r7, lr}
328-
; ARMOPTNONE-NEXT: add r7, sp, #8
329-
; ARMOPTNONE-NEXT: push {r8, r10, r11}
330-
; ARMOPTNONE-NEXT: sub sp, sp, #24
331-
; ARMOPTNONE-NEXT: str r0, [sp, #4] @ 4-byte Spill
332-
; ARMOPTNONE-NEXT: str r2, [sp, #8] @ 4-byte Spill
333-
; ARMOPTNONE-NEXT: str r1, [sp, #12] @ 4-byte Spill
334-
; ARMOPTNONE-NEXT: dmb ish
335-
; ARMOPTNONE-NEXT: ldr r1, [r0]
336-
; ARMOPTNONE-NEXT: ldr r0, [r0, #4]
337-
; ARMOPTNONE-NEXT: str r1, [sp, #16] @ 4-byte Spill
338-
; ARMOPTNONE-NEXT: str r0, [sp, #20] @ 4-byte Spill
327+
; ARMOPTNONE-NEXT: push {r4, r5, r7, r8, r10, r11, lr}
328+
; ARMOPTNONE-NEXT: add r7, sp, #20
329+
; ARMOPTNONE-NEXT: sub sp, sp, #24
330+
; ARMOPTNONE-NEXT: str r0, [sp, #4] @ 4-byte Spill
331+
; ARMOPTNONE-NEXT: str r2, [sp, #8] @ 4-byte Spill
332+
; ARMOPTNONE-NEXT: str r1, [sp, #12] @ 4-byte Spill
333+
; ARMOPTNONE-NEXT: dmb ish
334+
; ARMOPTNONE-NEXT: ldr r1, [r0]
335+
; ARMOPTNONE-NEXT: ldr r0, [r0, #4]
336+
; ARMOPTNONE-NEXT: str r1, [sp, #16] @ 4-byte Spill
337+
; ARMOPTNONE-NEXT: str r0, [sp, #20] @ 4-byte Spill
339338
; ARMOPTNONE-NEXT: b LBB5_1
340339
; ARMOPTNONE-NEXT: LBB5_1: @ %atomicrmw.start
341340
; ARMOPTNONE-NEXT: @ =>This Loop Header: Depth=1
@@ -382,8 +381,7 @@ define void @test_old_store_64bit(ptr %p, i64 %v) {
382381
; ARMOPTNONE-NEXT: LBB5_5: @ %atomicrmw.end
383382
; ARMOPTNONE-NEXT: dmb ish
384383
; ARMOPTNONE-NEXT: sub sp, r7, #20
385-
; ARMOPTNONE-NEXT: pop {r8, r10, r11}
386-
; ARMOPTNONE-NEXT: pop {r4, r5, r7, pc}
384+
; ARMOPTNONE-NEXT: pop {r4, r5, r7, r8, r10, r11, pc}
387385
;
388386
; THUMBTWO-LABEL: test_old_store_64bit:
389387
; THUMBTWO: @ %bb.0:
@@ -864,20 +862,19 @@ define void @store_atomic_f64__seq_cst(ptr %ptr, double %val1) {
864862
;
865863
; ARMOPTNONE-LABEL: store_atomic_f64__seq_cst:
866864
; ARMOPTNONE: @ %bb.0:
867-
; ARMOPTNONE-NEXT: push {r4, r5, r7, lr}
868-
; ARMOPTNONE-NEXT: add r7, sp, #8
869-
; ARMOPTNONE-NEXT: push {r8, r10, r11}
870-
; ARMOPTNONE-NEXT: sub sp, sp, #24
871-
; ARMOPTNONE-NEXT: str r0, [sp, #4] @ 4-byte Spill
872-
; ARMOPTNONE-NEXT: vmov d16, r1, r2
873-
; ARMOPTNONE-NEXT: vmov r1, r2, d16
874-
; ARMOPTNONE-NEXT: str r2, [sp, #8] @ 4-byte Spill
875-
; ARMOPTNONE-NEXT: str r1, [sp, #12] @ 4-byte Spill
876-
; ARMOPTNONE-NEXT: dmb ish
877-
; ARMOPTNONE-NEXT: ldr r1, [r0]
878-
; ARMOPTNONE-NEXT: ldr r0, [r0, #4]
879-
; ARMOPTNONE-NEXT: str r1, [sp, #16] @ 4-byte Spill
880-
; ARMOPTNONE-NEXT: str r0, [sp, #20] @ 4-byte Spill
865+
; ARMOPTNONE-NEXT: push {r4, r5, r7, r8, r10, r11, lr}
866+
; ARMOPTNONE-NEXT: add r7, sp, #20
867+
; ARMOPTNONE-NEXT: sub sp, sp, #24
868+
; ARMOPTNONE-NEXT: str r0, [sp, #4] @ 4-byte Spill
869+
; ARMOPTNONE-NEXT: vmov d16, r1, r2
870+
; ARMOPTNONE-NEXT: vmov r1, r2, d16
871+
; ARMOPTNONE-NEXT: str r2, [sp, #8] @ 4-byte Spill
872+
; ARMOPTNONE-NEXT: str r1, [sp, #12] @ 4-byte Spill
873+
; ARMOPTNONE-NEXT: dmb ish
874+
; ARMOPTNONE-NEXT: ldr r1, [r0]
875+
; ARMOPTNONE-NEXT: ldr r0, [r0, #4]
876+
; ARMOPTNONE-NEXT: str r1, [sp, #16] @ 4-byte Spill
877+
; ARMOPTNONE-NEXT: str r0, [sp, #20] @ 4-byte Spill
881878
; ARMOPTNONE-NEXT: b LBB13_1
882879
; ARMOPTNONE-NEXT: LBB13_1: @ %atomicrmw.start
883880
; ARMOPTNONE-NEXT: @ =>This Loop Header: Depth=1
@@ -924,8 +921,7 @@ define void @store_atomic_f64__seq_cst(ptr %ptr, double %val1) {
924921
; ARMOPTNONE-NEXT: LBB13_5: @ %atomicrmw.end
925922
; ARMOPTNONE-NEXT: dmb ish
926923
; ARMOPTNONE-NEXT: sub sp, r7, #20
927-
; ARMOPTNONE-NEXT: pop {r8, r10, r11}
928-
; ARMOPTNONE-NEXT: pop {r4, r5, r7, pc}
924+
; ARMOPTNONE-NEXT: pop {r4, r5, r7, r8, r10, r11, pc}
929925
;
930926
; THUMBTWO-LABEL: store_atomic_f64__seq_cst:
931927
; THUMBTWO: @ %bb.0:

0 commit comments

Comments
 (0)