Search results

[SDAG] Remove IndexType manipulation in getUniformBase and callers

llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well

Status: Open (in progress).

llvm/llvm-projectnumber 151578

#151578 In llvm/llvm-project;

· preames opened on Jul 31, 2025

[DAG] Fold trunc(abdu(x,y)) and trunc(abds(x,y)) if they have sufficient leading zero/sign bits

backend:AArch64

llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well

Status: Open (in progress).

llvm/llvm-projectnumber 151471

#151471 In llvm/llvm-project;

· woruyu opened on Jul 31, 2025

LLVM 21.1.0: Unable to expand result for ppcf128 with ISD::AssertNoFPClass

backend:PowerPC

crashPrefer [crash-on-valid] or [crash-on-invalid]Prefer [crash-on-valid] or [crash-on-invalid]

llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well

Status: Open.

Bug

#151375 In llvm/llvm-project;

· amy-kwan opened on Jul 30, 2025

· 

LLVM 21.x Release

[ARM] Remove <code>UnsafeFPMath</code> uses

backend:ARM

llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well

Status: Open (in progress).

llvm/llvm-projectnumber 151275

#151275 In llvm/llvm-project;

· paperchalice opened on Jul 30, 2025

[IR] Allow poison argument to lifetime markers

compiler-rt:sanitizer

llvm:analysisIncludes value tracking, cost tables and constant foldingIncludes value tracking, cost tables and constant folding

llvm:globalisel

llvm:instcombineCovers the InstCombine, InstSimplify and AggressiveInstCombine passesCovers the InstCombine, InstSimplify and AggressiveInstCombine passes

llvm:ir

llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well

llvm:transforms

Status: Open (in progress).

llvm/llvm-projectnumber 151148

#151148 In llvm/llvm-project;

· nikic opened on Jul 29, 2025

[DAGCombiner] Add combine for vector interleave of splats

backend:AArch64

backend:RISC-V

llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well

Status: Open (in progress).

llvm/llvm-projectnumber 151110

#151110 In llvm/llvm-project;

· david-arm opened on Jul 29, 2025

[DAG] Always use stack to promote bitcast when the source is vector

backend:AMDGPU

llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well

Status: Open (in progress).

llvm/llvm-projectnumber 151065

#151065 In llvm/llvm-project;

· mshockwave opened on Jul 29, 2025

[RISCV][GlobalISel][TargetLowering] Change SSUBO to do (LHS &lt; RHS) XOR (RESULT &lt; 0)

backend:AMDGPU

backend:RISC-V

backend:X86

llvm:globalisel

llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well

Status: Open (in progress).

llvm/llvm-projectnumber 150872

#150872 In llvm/llvm-project;

· AZero13 opened on Jul 28, 2025

[SelectionDAG] Detect impossible conditions using known bits analysis

backend:AArch64

backend:AMDGPU

backend:ARM

backend:Hexagon

backend:loongarch

backend:RISC-V

backend:X86

llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well

Status: Draft (not ready).

llvm/llvm-projectnumber 150715

#150715 In llvm/llvm-project;

· AZero13 opened on Jul 25, 2025

[LLVM][DAGCombiner] fold (shl (X * vscale(C0)), C1) -&gt; (X * vscale(C0 &lt;&lt; C1)).

backend:AArch64

llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well

llvm:transforms

Status: Open (in progress).

llvm/llvm-projectnumber 150651

#150651 In llvm/llvm-project;

· paulwalker-arm opened on Jul 25, 2025

release/21.x: [DAG] visitFREEZE - limit freezing of multiple operands

backend:AMDGPU

backend:NVPTX

backend:PowerPC

backend:RISC-V

backend:SystemZ

backend:X86

llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well

Status: Open (in progress).

llvm/llvm-projectnumber 150425

#150425 In llvm/llvm-project;

· RKSimon opened on Jul 24, 2025

[DAG] combineVSelectWithAllOnesOrZeros - missing freeze

backend:AArch64

backend:X86

llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well

Status: Open (in progress).

llvm/llvm-projectnumber 150388

#150388 In llvm/llvm-project;

· woruyu opened on Jul 24, 2025