diff --git a/llvm/lib/Target/AMDGPU/AMDGPUGISel.td b/llvm/lib/Target/AMDGPU/AMDGPUGISel.td index 2b85024a9b40b..92ada7e84ed5f 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUGISel.td +++ b/llvm/lib/Target/AMDGPU/AMDGPUGISel.td @@ -51,9 +51,9 @@ def gi_vop3pmodsdot : GIComplexOperandMatcher, GIComplexPatternEquiv; -def gi_dotiuvop3pmods : - GIComplexOperandMatcher, - GIComplexPatternEquiv; +def gi_vop3pmodsneg : + GIComplexOperandMatcher, + GIComplexPatternEquiv; def gi_wmmaopselvop3pmods : GIComplexOperandMatcher, diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp index 41462d7a133ed..e753b75dbbf49 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp @@ -3009,7 +3009,7 @@ bool AMDGPUDAGToDAGISel::SelectVOP3PModsDOT(SDValue In, SDValue &Src, return SelectVOP3PMods(In, Src, SrcMods, true); } -bool AMDGPUDAGToDAGISel::SelectDotIUVOP3PMods(SDValue In, SDValue &Src) const { +bool AMDGPUDAGToDAGISel::SelectVOP3PModsNeg(SDValue In, SDValue &Src) const { const ConstantSDNode *C = cast(In); // Literal i1 value set in intrinsic, represents SrcMods for the next operand. // 1 promotes packed values to signed, 0 treats them as unsigned. diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h index df4a211d42a09..8645490f0b16f 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h @@ -237,7 +237,7 @@ class AMDGPUDAGToDAGISel : public SelectionDAGISel { bool IsDOT = false) const; bool SelectVOP3PModsDOT(SDValue In, SDValue &Src, SDValue &SrcMods) const; - bool SelectDotIUVOP3PMods(SDValue In, SDValue &Src) const; + bool SelectVOP3PModsNeg(SDValue In, SDValue &Src) const; bool SelectWMMAOpSelVOP3PMods(SDValue In, SDValue &Src) const; bool SelectVOP3OpSel(SDValue In, SDValue &Src, SDValue &SrcMods) const; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp index ad8dcda93c365..16642a76288c0 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp @@ -3927,7 +3927,7 @@ AMDGPUInstructionSelector::selectVOP3PModsDOT(MachineOperand &Root) const { } InstructionSelector::ComplexRendererFns -AMDGPUInstructionSelector::selectDotIUVOP3PMods(MachineOperand &Root) const { +AMDGPUInstructionSelector::selectVOP3PModsNeg(MachineOperand &Root) const { // Literal i1 value set in intrinsic, represents SrcMods for the next operand. // Value is in Imm operand as i1 sign extended to int64_t. // 1(-1) promotes packed values to signed, 0 treats them as unsigned. diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h index ab7cc0a6beb8c..9b39ebdf37717 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h @@ -194,7 +194,7 @@ class AMDGPUInstructionSelector final : public InstructionSelector { selectVOP3PModsDOT(MachineOperand &Root) const; InstructionSelector::ComplexRendererFns - selectDotIUVOP3PMods(MachineOperand &Root) const; + selectVOP3PModsNeg(MachineOperand &Root) const; InstructionSelector::ComplexRendererFns selectWMMAOpSelVOP3PMods(MachineOperand &Root) const; diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td index 04c92155f5aad..6e87c727462ec 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td @@ -1353,7 +1353,7 @@ def VOP3OMods : ComplexPattern; def VOP3PMods : ComplexPattern; def VOP3PModsDOT : ComplexPattern; -def DotIUVOP3PMods : ComplexPattern; +def VOP3PModsNeg : ComplexPattern; def WMMAOpSelVOP3PMods : ComplexPattern; def VOP3OpSel : ComplexPattern; diff --git a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td index e9d6f67aee164..9c0069a37eadc 100644 --- a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td +++ b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td @@ -415,8 +415,8 @@ multiclass VOP3PDOTIUInst { null_frag, 1>; // Dot-iu instructions consider input as signed if imod neg bits are set. Thus // Dot-iu Intrinsics have extra operands and require separate codegen pattern. - def : GCNPat < (intrinsic_node (DotIUVOP3PMods i32:$src0_mods), i32:$src0, - (DotIUVOP3PMods i32:$src1_mods), i32:$src1, + def : GCNPat < (intrinsic_node (VOP3PModsNeg i32:$src0_mods), i32:$src0, + (VOP3PModsNeg i32:$src1_mods), i32:$src1, i32:$src2, (i1 timm:$clamp)), (!cast(NAME) $src0_mods, i32:$src0, $src1_mods, i32:$src1, @@ -812,8 +812,8 @@ class WMMAOpSelPat : class WMMAUIClampPat : GCNPat < (P.DstVT (node - (DotIUVOP3PMods i32:$src0_modifiers), (P.Src0VT P.Src0VT:$src0), - (DotIUVOP3PMods i32:$src1_modifiers), (P.Src1VT P.Src1VT:$src1), + (VOP3PModsNeg i32:$src0_modifiers), (P.Src0VT P.Src0VT:$src0), + (VOP3PModsNeg i32:$src1_modifiers), (P.Src1VT P.Src1VT:$src1), (P.Src2VT P.Src2VT:$src2), (i1 timm:$clamp) )), (P.DstVT (Inst i32:$src0_modifiers, P.Src0VT:$src0, i32:$src1_modifiers, P.Src1VT:$src1, (i32 8), P.Src2VT:$src2, i1:$clamp))