From 3f6ce2959d681eba9e30c038bffcb0fe36e5ae85 Mon Sep 17 00:00:00 2001 From: CaiWeiran <168266995+CaiWeiran@users.noreply.github.com> Date: Mon, 14 Jul 2025 11:41:23 +0800 Subject: [PATCH 01/10] Update dwarf-mixed-versions-lto.rs Fix tests/assembly/dwarf-mixed-versions-lto.rs test failure on riscv64. --- tests/assembly/dwarf-mixed-versions-lto.rs | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tests/assembly/dwarf-mixed-versions-lto.rs b/tests/assembly/dwarf-mixed-versions-lto.rs index 9910a6e2f5fcc..e04a18133fa66 100644 --- a/tests/assembly/dwarf-mixed-versions-lto.rs +++ b/tests/assembly/dwarf-mixed-versions-lto.rs @@ -15,6 +15,6 @@ fn main() { } // CHECK: .section .debug_info -// CHECK-NOT: {{\.(short|hword|2byte)}} 2 -// CHECK-NOT: {{\.(short|hword|2byte)}} 4 -// CHECK: {{\.(short|hword|2byte)}} 5 +// CHECK-NOT: {{\.(short|hword|2byte|half)}} 2 +// CHECK-NOT: {{\.(short|hword|2byte|half)}} 4 +// CHECK: {{\.(short|hword|2byte|half)}} 5 From cd818c7e91910619fd72d3d159660ea7eb7999a2 Mon Sep 17 00:00:00 2001 From: CaiWeiran <168266995+CaiWeiran@users.noreply.github.com> Date: Mon, 14 Jul 2025 11:42:32 +0800 Subject: [PATCH 02/10] Update const-vector.rs Fix tests/codegen/const-vector.rs test failure on riscv64. --- tests/codegen/const-vector.rs | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/codegen/const-vector.rs b/tests/codegen/const-vector.rs index 42921442e039f..53b8844d133b1 100644 --- a/tests/codegen/const-vector.rs +++ b/tests/codegen/const-vector.rs @@ -15,6 +15,7 @@ #![feature(arm_target_feature)] #![feature(mips_target_feature)] #![allow(non_camel_case_types)] +#![feature(riscv_target_feature)] // Setting up structs that can be used as const vectors #[repr(simd)] @@ -51,6 +52,7 @@ extern "unadjusted" { #[cfg_attr(target_arch = "arm", target_feature(enable = "neon"))] #[cfg_attr(target_arch = "x86", target_feature(enable = "sse"))] #[cfg_attr(target_arch = "mips", target_feature(enable = "msa"))] +#[cfg_attr(target_arch = "riscv64", target_feature(enable = "v"))] pub fn do_call() { unsafe { // CHECK: call void @test_i8x2(<2 x i8> From cb8036088d61078a3f9aaa1f8f01468bdc3e1cca Mon Sep 17 00:00:00 2001 From: CaiWeiran <168266995+CaiWeiran@users.noreply.github.com> Date: Mon, 14 Jul 2025 11:43:37 +0800 Subject: [PATCH 03/10] Update enum-aggregate.rs Fix tests/codegen/enum/enum-aggregate.rs test failure on riscv64. --- tests/codegen/enum/enum-aggregate.rs | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tests/codegen/enum/enum-aggregate.rs b/tests/codegen/enum/enum-aggregate.rs index 0161e5f3fa1a1..8774098701c20 100644 --- a/tests/codegen/enum/enum-aggregate.rs +++ b/tests/codegen/enum/enum-aggregate.rs @@ -27,7 +27,7 @@ fn make_none_bool() -> Option { #[no_mangle] fn make_some_ordering(x: Ordering) -> Option { - // CHECK-LABEL: i8 @make_some_ordering(i8 %x) + // CHECK-LABEL: i8 @make_some_ordering(i8 {{.*}}%x) // CHECK-NEXT: start: // CHECK-NEXT: ret i8 %x Some(x) @@ -35,7 +35,7 @@ fn make_some_ordering(x: Ordering) -> Option { #[no_mangle] fn make_some_u16(x: u16) -> Option { - // CHECK-LABEL: { i16, i16 } @make_some_u16(i16 %x) + // CHECK-LABEL: { i16, i16 } @make_some_u16(i16 {{.*}}%x) // CHECK-NEXT: start: // CHECK-NEXT: %0 = insertvalue { i16, i16 } { i16 1, i16 poison }, i16 %x, 1 // CHECK-NEXT: ret { i16, i16 } %0 @@ -52,7 +52,7 @@ fn make_none_u16() -> Option { #[no_mangle] fn make_some_nzu32(x: NonZero) -> Option> { - // CHECK-LABEL: i32 @make_some_nzu32(i32 %x) + // CHECK-LABEL: i32 @make_some_nzu32(i32 {{.*}}%x) // CHECK-NEXT: start: // CHECK-NEXT: ret i32 %x Some(x) @@ -114,7 +114,7 @@ fn make_uninhabited_err_indirectly(n: Never) -> Result { fn make_fully_uninhabited_result(v: u32, n: Never) -> Result<(u32, Never), (Never, u32)> { // Actually reaching this would be UB, so we don't actually build a result. - // CHECK-LABEL: { i32, i32 } @make_fully_uninhabited_result(i32 %v) + // CHECK-LABEL: { i32, i32 } @make_fully_uninhabited_result(i32 {{.*}}%v) // CHECK-NEXT: start: // CHECK-NEXT: call void @llvm.trap() // CHECK-NEXT: call void @llvm.trap() From 326780b13ae315fb9e27475d3c8b1aa10e4f2e0c Mon Sep 17 00:00:00 2001 From: CaiWeiran <168266995+CaiWeiran@users.noreply.github.com> Date: Mon, 14 Jul 2025 11:45:14 +0800 Subject: [PATCH 04/10] Update extract-insert-dyn.rs Fix tests/codegen/simd/extract-insert-dyn.rs test failure on riscv64. --- tests/codegen/simd/extract-insert-dyn.rs | 27 ++++++++++++++++-------- 1 file changed, 18 insertions(+), 9 deletions(-) diff --git a/tests/codegen/simd/extract-insert-dyn.rs b/tests/codegen/simd/extract-insert-dyn.rs index 729f0145314a3..9c17b82e55352 100644 --- a/tests/codegen/simd/extract-insert-dyn.rs +++ b/tests/codegen/simd/extract-insert-dyn.rs @@ -5,7 +5,8 @@ repr_simd, arm_target_feature, mips_target_feature, - s390x_target_feature + s390x_target_feature, + riscv_target_feature )] #![no_std] #![crate_type = "lib"] @@ -25,97 +26,105 @@ pub struct u32x16([u32; 16]); pub struct i8x16([i8; 16]); // CHECK-LABEL: dyn_simd_extract -// CHECK: extractelement <16 x i8> %x, i32 %idx +// CHECK: extractelement <16 x i8> %[[TEMP:.+]], i32 %idx #[no_mangle] #[cfg_attr(target_family = "wasm", target_feature(enable = "simd128"))] #[cfg_attr(target_arch = "arm", target_feature(enable = "neon"))] #[cfg_attr(target_arch = "x86", target_feature(enable = "sse"))] #[cfg_attr(target_arch = "mips", target_feature(enable = "msa"))] #[cfg_attr(target_arch = "s390x", target_feature(enable = "vector"))] +#[cfg_attr(target_arch = "riscv64", target_feature(enable = "v"))] unsafe extern "C" fn dyn_simd_extract(x: i8x16, idx: u32) -> i8 { simd_extract_dyn(x, idx) } // CHECK-LABEL: literal_dyn_simd_extract -// CHECK: extractelement <16 x i8> %x, i32 7 +// CHECK: extractelement <16 x i8> %[[TEMP:.+]], i32 7 #[no_mangle] #[cfg_attr(target_family = "wasm", target_feature(enable = "simd128"))] #[cfg_attr(target_arch = "arm", target_feature(enable = "neon"))] #[cfg_attr(target_arch = "x86", target_feature(enable = "sse"))] #[cfg_attr(target_arch = "mips", target_feature(enable = "msa"))] #[cfg_attr(target_arch = "s390x", target_feature(enable = "vector"))] +#[cfg_attr(target_arch = "riscv64", target_feature(enable = "v"))] unsafe extern "C" fn literal_dyn_simd_extract(x: i8x16) -> i8 { simd_extract_dyn(x, 7) } // CHECK-LABEL: const_dyn_simd_extract -// CHECK: extractelement <16 x i8> %x, i32 7 +// CHECK: extractelement <16 x i8> %[[TEMP:.+]], i32 7 #[no_mangle] #[cfg_attr(target_family = "wasm", target_feature(enable = "simd128"))] #[cfg_attr(target_arch = "arm", target_feature(enable = "neon"))] #[cfg_attr(target_arch = "x86", target_feature(enable = "sse"))] #[cfg_attr(target_arch = "mips", target_feature(enable = "msa"))] #[cfg_attr(target_arch = "s390x", target_feature(enable = "vector"))] +#[cfg_attr(target_arch = "riscv64", target_feature(enable = "v"))] unsafe extern "C" fn const_dyn_simd_extract(x: i8x16) -> i8 { simd_extract_dyn(x, const { 3 + 4 }) } // CHECK-LABEL: const_simd_extract -// CHECK: extractelement <16 x i8> %x, i32 7 +// CHECK: extractelement <16 x i8> %[[TEMP:.+]], i32 7 #[no_mangle] #[cfg_attr(target_family = "wasm", target_feature(enable = "simd128"))] #[cfg_attr(target_arch = "arm", target_feature(enable = "neon"))] #[cfg_attr(target_arch = "x86", target_feature(enable = "sse"))] #[cfg_attr(target_arch = "mips", target_feature(enable = "msa"))] #[cfg_attr(target_arch = "s390x", target_feature(enable = "vector"))] +#[cfg_attr(target_arch = "riscv64", target_feature(enable = "v"))] unsafe extern "C" fn const_simd_extract(x: i8x16) -> i8 { simd_extract(x, const { 3 + 4 }) } // CHECK-LABEL: dyn_simd_insert -// CHECK: insertelement <16 x i8> %x, i8 %e, i32 %idx +// CHECK: insertelement <16 x i8> %[[TEMP:.+]], i8 %e, i32 %idx #[no_mangle] #[cfg_attr(target_family = "wasm", target_feature(enable = "simd128"))] #[cfg_attr(target_arch = "arm", target_feature(enable = "neon"))] #[cfg_attr(target_arch = "x86", target_feature(enable = "sse"))] #[cfg_attr(target_arch = "mips", target_feature(enable = "msa"))] #[cfg_attr(target_arch = "s390x", target_feature(enable = "vector"))] +#[cfg_attr(target_arch = "riscv64", target_feature(enable = "v"))] unsafe extern "C" fn dyn_simd_insert(x: i8x16, e: i8, idx: u32) -> i8x16 { simd_insert_dyn(x, idx, e) } // CHECK-LABEL: literal_dyn_simd_insert -// CHECK: insertelement <16 x i8> %x, i8 %e, i32 7 +// CHECK: insertelement <16 x i8> %[[TEMP:.+]], i8 %e, i32 7 #[no_mangle] #[cfg_attr(target_family = "wasm", target_feature(enable = "simd128"))] #[cfg_attr(target_arch = "arm", target_feature(enable = "neon"))] #[cfg_attr(target_arch = "x86", target_feature(enable = "sse"))] #[cfg_attr(target_arch = "mips", target_feature(enable = "msa"))] #[cfg_attr(target_arch = "s390x", target_feature(enable = "vector"))] +#[cfg_attr(target_arch = "riscv64", target_feature(enable = "v"))] unsafe extern "C" fn literal_dyn_simd_insert(x: i8x16, e: i8) -> i8x16 { simd_insert_dyn(x, 7, e) } // CHECK-LABEL: const_dyn_simd_insert -// CHECK: insertelement <16 x i8> %x, i8 %e, i32 7 +// CHECK: insertelement <16 x i8> %[[TEMP:.+]], i8 %e, i32 7 #[no_mangle] #[cfg_attr(target_family = "wasm", target_feature(enable = "simd128"))] #[cfg_attr(target_arch = "arm", target_feature(enable = "neon"))] #[cfg_attr(target_arch = "x86", target_feature(enable = "sse"))] #[cfg_attr(target_arch = "mips", target_feature(enable = "msa"))] #[cfg_attr(target_arch = "s390x", target_feature(enable = "vector"))] +#[cfg_attr(target_arch = "riscv64", target_feature(enable = "v"))] unsafe extern "C" fn const_dyn_simd_insert(x: i8x16, e: i8) -> i8x16 { simd_insert_dyn(x, const { 3 + 4 }, e) } // CHECK-LABEL: const_simd_insert -// CHECK: insertelement <16 x i8> %x, i8 %e, i32 7 +// CHECK: insertelement <16 x i8> %[[TEMP:.+]], i8 %e, i32 7 #[no_mangle] #[cfg_attr(target_family = "wasm", target_feature(enable = "simd128"))] #[cfg_attr(target_arch = "arm", target_feature(enable = "neon"))] #[cfg_attr(target_arch = "x86", target_feature(enable = "sse"))] #[cfg_attr(target_arch = "mips", target_feature(enable = "msa"))] #[cfg_attr(target_arch = "s390x", target_feature(enable = "vector"))] +#[cfg_attr(target_arch = "riscv64", target_feature(enable = "v"))] unsafe extern "C" fn const_simd_insert(x: i8x16, e: i8) -> i8x16 { simd_insert(x, const { 3 + 4 }, e) } From 437b2069ea6f329fd6a9b5d88b29fb2c3abf093f Mon Sep 17 00:00:00 2001 From: CaiWeiran <168266995+CaiWeiran@users.noreply.github.com> Date: Mon, 14 Jul 2025 11:46:29 +0800 Subject: [PATCH 05/10] Update transmute-scalar.rs Fix tests/codegen/transmute-scalar.rs test failure on riscv64. --- tests/codegen/transmute-scalar.rs | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/tests/codegen/transmute-scalar.rs b/tests/codegen/transmute-scalar.rs index ce1b0558b2eec..c8819e0a8b5cd 100644 --- a/tests/codegen/transmute-scalar.rs +++ b/tests/codegen/transmute-scalar.rs @@ -2,7 +2,7 @@ //@ compile-flags: -C opt-level=0 -C no-prepopulate-passes #![crate_type = "lib"] -#![feature(no_core, repr_simd, arm_target_feature, mips_target_feature, s390x_target_feature)] +#![feature(no_core, repr_simd, arm_target_feature, mips_target_feature, s390x_target_feature, riscv_target_feature)] #![no_core] extern crate minicore; @@ -79,7 +79,7 @@ pub fn bool_to_fake_bool_signed(b: bool) -> FakeBoolSigned { unsafe { mem::transmute(b) } } -// CHECK-LABEL: define{{.*}}i1 @fake_bool_signed_to_bool(i8 %b) +// CHECK-LABEL: define{{.*}}i1 @fake_bool_signed_to_bool(i8 {{.*}}%b) // CHECK: %_0 = trunc nuw i8 %b to i1 // CHECK-NEXT: ret i1 %_0 #[no_mangle] @@ -110,34 +110,36 @@ pub fn fake_bool_unsigned_to_bool(b: FakeBoolUnsigned) -> bool { #[repr(simd)] struct S([i64; 1]); -// CHECK-LABEL: define{{.*}}i64 @single_element_simd_to_scalar(<1 x i64> %b) +// CHECK-LABEL: define{{.*}}i64 @single_element_simd_to_scalar({{.*}}i64 %{{.*}}) // CHECK-NEXT: start: // CHECK-NEXT: %[[RET:.+]] = alloca [8 x i8] -// CHECK-NEXT: store <1 x i64> %b, ptr %[[RET]] -// CHECK-NEXT: %[[TEMP:.+]] = load i64, ptr %[[RET]] -// CHECK-NEXT: ret i64 %[[TEMP]] +// CHECK: store <1 x i64> %[[TEMP:.+]], ptr %[[RET]] +// CHECK: %[[TEMP:.+]] = load i64, ptr %[[RET]] +// CHECK: ret i64 %[[TEMP]] #[no_mangle] #[cfg_attr(target_family = "wasm", target_feature(enable = "simd128"))] #[cfg_attr(target_arch = "arm", target_feature(enable = "neon"))] #[cfg_attr(target_arch = "x86", target_feature(enable = "sse"))] #[cfg_attr(target_arch = "mips", target_feature(enable = "msa"))] #[cfg_attr(target_arch = "s390x", target_feature(enable = "vector"))] +#[cfg_attr(target_arch = "riscv64", target_feature(enable = "v"))] pub extern "C" fn single_element_simd_to_scalar(b: S) -> i64 { unsafe { mem::transmute(b) } } -// CHECK-LABEL: define{{.*}}<1 x i64> @scalar_to_single_element_simd(i64 %b) +// CHECK-LABEL: define{{.*}}i64{{.*}} @scalar_to_single_element_simd(i64 %b) // CHECK-NEXT: start: // CHECK-NEXT: %[[RET:.+]] = alloca [8 x i8] // CHECK-NEXT: store i64 %b, ptr %[[RET]] -// CHECK-NEXT: %[[TEMP:.+]] = load <1 x i64>, ptr %[[RET]] -// CHECK-NEXT: ret <1 x i64> %[[TEMP]] +// CHECK-NEXT: %[[TEMP:.+]] = load{{.*}}i64{{.*}}, ptr %[[RET]] +// CHECK-NEXT: ret {{.*}}i64{{.*}}%[[TEMP]] #[no_mangle] #[cfg_attr(target_family = "wasm", target_feature(enable = "simd128"))] #[cfg_attr(target_arch = "arm", target_feature(enable = "neon"))] #[cfg_attr(target_arch = "x86", target_feature(enable = "sse"))] #[cfg_attr(target_arch = "mips", target_feature(enable = "msa"))] #[cfg_attr(target_arch = "s390x", target_feature(enable = "vector"))] +#[cfg_attr(target_arch = "riscv64", target_feature(enable = "v"))] pub extern "C" fn scalar_to_single_element_simd(b: i64) -> S { unsafe { mem::transmute(b) } } From c162f6b1deb3229030cb59c01987d169f36657bf Mon Sep 17 00:00:00 2001 From: CaiWeiran <168266995+CaiWeiran@users.noreply.github.com> Date: Mon, 14 Jul 2025 11:47:23 +0800 Subject: [PATCH 06/10] Update uninhabited-transparent-return-abi.rs Fix tests/codegen/uninhabited-transparent-return-abi.rs test failure on riscv64. --- tests/codegen/uninhabited-transparent-return-abi.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/codegen/uninhabited-transparent-return-abi.rs b/tests/codegen/uninhabited-transparent-return-abi.rs index face1577c3f69..e001d0aaf06c0 100644 --- a/tests/codegen/uninhabited-transparent-return-abi.rs +++ b/tests/codegen/uninhabited-transparent-return-abi.rs @@ -36,7 +36,7 @@ pub fn test_uninhabited_ret_by_ref() { pub fn test_uninhabited_ret_by_ref_with_arg(rsi: u32) { // CHECK: %_2 = alloca [24 x i8], align {{8|4}} // CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 24, ptr nonnull %_2) - // CHECK-NEXT: call void @opaque_with_arg({{.*}} sret([24 x i8]) {{.*}} %_2, i32 noundef %rsi) #2 + // CHECK-NEXT: call void @opaque_with_arg({{.*}} sret([24 x i8]) {{.*}} %_2, i32 noundef{{.*}}%rsi) #2 // CHECK-NEXT: unreachable unsafe { opaque_with_arg(rsi); From 92734625c9105b651c876dd9edece980cbd29a14 Mon Sep 17 00:00:00 2001 From: CaiWeiran <168266995+CaiWeiran@users.noreply.github.com> Date: Mon, 14 Jul 2025 12:36:51 +0800 Subject: [PATCH 07/10] Update transmute-scalar.rs Fix tidy check error. --- tests/codegen/transmute-scalar.rs | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tests/codegen/transmute-scalar.rs b/tests/codegen/transmute-scalar.rs index c8819e0a8b5cd..d187e794a4399 100644 --- a/tests/codegen/transmute-scalar.rs +++ b/tests/codegen/transmute-scalar.rs @@ -2,8 +2,9 @@ //@ compile-flags: -C opt-level=0 -C no-prepopulate-passes #![crate_type = "lib"] -#![feature(no_core, repr_simd, arm_target_feature, mips_target_feature, s390x_target_feature, riscv_target_feature)] +#![feature(no_core, repr_simd, arm_target_feature, mips_target_feature, s390x_target_feature)] #![no_core] +#![feature(riscv_target_feature)] extern crate minicore; use minicore::*; From 77e17ff18e4258ec7b494302d4acef9f4a442c39 Mon Sep 17 00:00:00 2001 From: CaiWeiran <168266995+CaiWeiran@users.noreply.github.com> Date: Mon, 14 Jul 2025 13:38:04 +0800 Subject: [PATCH 08/10] Update transmute-scalar.rs Fix regex matching error. --- tests/codegen/transmute-scalar.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/codegen/transmute-scalar.rs b/tests/codegen/transmute-scalar.rs index d187e794a4399..c63daae610ff4 100644 --- a/tests/codegen/transmute-scalar.rs +++ b/tests/codegen/transmute-scalar.rs @@ -111,7 +111,7 @@ pub fn fake_bool_unsigned_to_bool(b: FakeBoolUnsigned) -> bool { #[repr(simd)] struct S([i64; 1]); -// CHECK-LABEL: define{{.*}}i64 @single_element_simd_to_scalar({{.*}}i64 %{{.*}}) +// CHECK-LABEL: define{{.*}}i64 @single_element_simd_to_scalar({{.*}}i64{{.*}}%{{.*}}) // CHECK-NEXT: start: // CHECK-NEXT: %[[RET:.+]] = alloca [8 x i8] // CHECK: store <1 x i64> %[[TEMP:.+]], ptr %[[RET]] From d464e5752e7a5f9a95d73c3513f948c4aee61bbf Mon Sep 17 00:00:00 2001 From: CaiWeiran <168266995+CaiWeiran@users.noreply.github.com> Date: Fri, 18 Jul 2025 09:09:23 +0800 Subject: [PATCH 09/10] Update rmake.rs Ignore cross-compile. --- tests/run-make/link-eh-frame-terminator/rmake.rs | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/run-make/link-eh-frame-terminator/rmake.rs b/tests/run-make/link-eh-frame-terminator/rmake.rs index 6bfae386ea1ab..06b77f011ece0 100644 --- a/tests/run-make/link-eh-frame-terminator/rmake.rs +++ b/tests/run-make/link-eh-frame-terminator/rmake.rs @@ -9,6 +9,7 @@ //@ ignore-32bit // Reason: the usage of a large array in the test causes an out-of-memory // error on 32 bit systems. +//@ ignore-cross-compile use run_make_support::{bin_name, llvm_objdump, run, rustc}; From 2593e13ae7ba2a91469d4445d51e0f9c7cc32228 Mon Sep 17 00:00:00 2001 From: Caiweiran Date: Fri, 18 Jul 2025 11:29:48 +0000 Subject: [PATCH 10/10] Revert "Update rmake.rs" This reverts commit d464e5752e7a5f9a95d73c3513f948c4aee61bbf. --- tests/run-make/link-eh-frame-terminator/rmake.rs | 1 - 1 file changed, 1 deletion(-) diff --git a/tests/run-make/link-eh-frame-terminator/rmake.rs b/tests/run-make/link-eh-frame-terminator/rmake.rs index 06b77f011ece0..6bfae386ea1ab 100644 --- a/tests/run-make/link-eh-frame-terminator/rmake.rs +++ b/tests/run-make/link-eh-frame-terminator/rmake.rs @@ -9,7 +9,6 @@ //@ ignore-32bit // Reason: the usage of a large array in the test causes an out-of-memory // error on 32 bit systems. -//@ ignore-cross-compile use run_make_support::{bin_name, llvm_objdump, run, rustc};