Unable to handle inline assembly ends with compat-branch on MIPS

[FlyGoat]

Currently LLVM unable to handle the situation that a inline Assembly ends with branch instruction and then compiler generate another CTI immediately.

It would leave compiler generated CTI in forbidden slot and crash at runtime.

Test case:

define i32 @foo0() nounwind {
entry:
  %0 = tail call i32 asm "1: addiu $0, $$0, 1; beqzc $0, 1b;", "=r"() nounwind
  ret i32 %0
}

Generate object file with:

llc -mtriple=mips64el-linux-gnuabi64 -mcpu=mips64r6 -filetype=obj ./broken-forbidden-slot.ll

Then dissemble with:

$ mips64el-linux-gnuabi64-objdump -d ./broken-forbidden-slot.o
./broken-forbidden-slot.o:     file format elf64-tradlittlemips


Disassembly of section .text:

0000000000000000 <foo0>:
   0:   24020001        li      v0,1
   4:   d85ffffe        beqzc   v0,0 <foo0>
   8:   d81f0000        jrc     ra

JRC lies in forbidden slot of BEQZC.

[llvmbot]

@llvm/issue-subscribers-backend-mips

[jrtc27]

Why is inline assembly relevant? GCC and Clang do the same thing for this https://godbolt.org/z/hrf5ndKhv. Is it just a case of teaching the .set reorder code to deal with forbidden slots like it does delay slots?

[FlyGoat]

Why is inline assembly relevant? GCC and Clang do the same thing for this https://godbolt.org/z/hrf5ndKhv. Is it just a case of teaching the .set reorder code to deal with forbidden slots like it does delay slots?

Ouch yes that's probably the root cause. I was only inspecting generated binary so I was not aware of those directives.

@wzssyqa Could you please make Ying Huang aware of that?