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[PowerPC][AIX] Using milicode for memcmp instead of libcall #147093

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[PowerPC][AIX] Using milicode for memcmp instead of libcall #147093

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a46d818
implement milicode memcmp
diggerlin Jun 27, 2025
cc21f3a
modify test case based on new behavious
diggerlin Jul 4, 2025
d835a24
address comment
diggerlin Jul 9, 2025
97837a2
remove useless code
diggerlin Jul 9, 2025
26e6c75
address comment
diggerlin Jul 10, 2025
0d8e632
minor change
diggerlin Jul 10, 2025
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3 changes: 3 additions & 0 deletions llvm/include/llvm/CodeGen/SelectionDAG.h
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Expand Up @@ -1257,6 +1257,9 @@ class SelectionDAG {
/// stack arguments from being clobbered.
LLVM_ABI SDValue getStackArgumentTokenFactor(SDValue Chain);

std::pair<SDValue, SDValue> getMemcmp(SDValue Chain, const SDLoc &dl,
SDValue Dst, SDValue Src, SDValue Size,
const CallInst *CI);
/* \p CI if not null is the memset call being lowered.
* \p OverrideTailCall is an optional parameter that can be used to override
* the tail call optimization decision. */
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5 changes: 2 additions & 3 deletions llvm/include/llvm/CodeGen/SelectionDAGTargetInfo.h
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Expand Up @@ -24,7 +24,7 @@
namespace llvm {

class SelectionDAG;

class CallInst;
//===----------------------------------------------------------------------===//
/// Targets can subclass this to parameterize the
/// SelectionDAG lowering and instruction selection process.
Expand Down Expand Up @@ -118,8 +118,7 @@ class SelectionDAGTargetInfo {
virtual std::pair<SDValue, SDValue>
EmitTargetCodeForMemcmp(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain,
SDValue Op1, SDValue Op2, SDValue Op3,
MachinePointerInfo Op1PtrInfo,
MachinePointerInfo Op2PtrInfo) const {
const CallInst *CI) const {
return std::make_pair(SDValue(), SDValue());
}

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3 changes: 3 additions & 0 deletions llvm/include/llvm/IR/RuntimeLibcalls.td
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Expand Up @@ -248,6 +248,7 @@ foreach FPTy = ["F32", "F64", "F128", "PPCF128"] in {
}

// Memory
def MEMCMP : RuntimeLibcall;
def MEMCPY : RuntimeLibcall;
def MEMMOVE : RuntimeLibcall;
def MEMSET : RuntimeLibcall;
Expand Down Expand Up @@ -1739,12 +1740,14 @@ defset list<RuntimeLibcallImpl> PPCRuntimeLibcalls = {
}

defset list<RuntimeLibcallImpl> PPC64AIXCallList = {
def ___memcmp64 : RuntimeLibcallImpl<MEMCMP>;
def ___memmove64 : RuntimeLibcallImpl<MEMCPY>;
def ___memset64 : RuntimeLibcallImpl<MEMSET>;
def ___bzero64 : RuntimeLibcallImpl<BZERO>;
}

defset list<RuntimeLibcallImpl> PPC32AIXCallList = {
def ___memcmp : RuntimeLibcallImpl<MEMCMP>;
def ___memmove : RuntimeLibcallImpl<MEMMOVE>;
def ___memset : RuntimeLibcallImpl<MEMSET>;
def ___bzero : RuntimeLibcallImpl<BZERO>;
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38 changes: 38 additions & 0 deletions llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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Expand Up @@ -8821,6 +8821,44 @@ static void checkAddrSpaceIsValidForLibcall(const TargetLowering *TLI,
}
}

std::pair<SDValue, SDValue>
SelectionDAG::getMemcmp(SDValue Chain, const SDLoc &dl, SDValue Mem0,
SDValue Mem1, SDValue Size, const CallInst *CI) {
const char *LibCallName = TLI->getLibcallName(RTLIB::MEMCMP);
if (!LibCallName)
return {};

// Emit a library call.
auto GetEntry = [](Type *Ty, SDValue &SDV) {
TargetLowering::ArgListEntry E;
E.Ty = Ty;
E.Node = SDV;
return E;
};

PointerType *PT = PointerType::getUnqual(*getContext());
TargetLowering::ArgListTy Args = {
GetEntry(PT, Mem0), GetEntry(PT, Mem1),
GetEntry(getDataLayout().getIntPtrType(*getContext()), Size)};

TargetLowering::CallLoweringInfo CLI(*this);
bool IsTailCall = false;
bool ReturnsFirstArg = CI && funcReturnsFirstArgOfCall(*CI);
IsTailCall = CI && CI->isTailCall() &&
isInTailCallPosition(*CI, getTarget(), ReturnsFirstArg);

CLI.setDebugLoc(dl)
.setChain(Chain)
.setLibCallee(
TLI->getLibcallCallingConv(RTLIB::MEMCMP),
Type::getInt32Ty(*getContext()),
getExternalSymbol(LibCallName, TLI->getPointerTy(getDataLayout())),
std::move(Args))
.setTailCall(IsTailCall);

return TLI->LowerCallTo(CLI);
}

SDValue SelectionDAG::getMemcpy(
SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size,
Align Alignment, bool isVol, bool AlwaysInline, const CallInst *CI,
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
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Expand Up @@ -9056,7 +9056,7 @@ bool SelectionDAGBuilder::visitMemCmpBCmpCall(const CallInst &I) {
const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo();
std::pair<SDValue, SDValue> Res = TSI.EmitTargetCodeForMemcmp(
DAG, getCurSDLoc(), DAG.getRoot(), getValue(LHS), getValue(RHS),
getValue(Size), MachinePointerInfo(LHS), MachinePointerInfo(RHS));
getValue(Size), &I);
if (Res.first.getNode()) {
processIntegerCallValue(I, Res.first, true);
PendingLoads.push_back(Res.second);
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6 changes: 6 additions & 0 deletions llvm/lib/Target/PowerPC/PPCSelectionDAGInfo.cpp
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Expand Up @@ -22,3 +22,9 @@ bool PPCSelectionDAGInfo::isTargetStrictFPOpcode(unsigned Opcode) const {
return Opcode >= PPCISD::FIRST_STRICTFP_OPCODE &&
Opcode <= PPCISD::LAST_STRICTFP_OPCODE;
}

std::pair<SDValue, SDValue> PPCSelectionDAGInfo::EmitTargetCodeForMemcmp(
SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, SDValue Op2,
SDValue Op3, const CallInst *CI) const {
return DAG.getMemcmp(Chain, dl, Op1, Op2, Op3, CI);
}
5 changes: 5 additions & 0 deletions llvm/lib/Target/PowerPC/PPCSelectionDAGInfo.h
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Expand Up @@ -20,6 +20,11 @@ class PPCSelectionDAGInfo : public SelectionDAGTargetInfo {
bool isTargetMemoryOpcode(unsigned Opcode) const override;

bool isTargetStrictFPOpcode(unsigned Opcode) const override;

std::pair<SDValue, SDValue>
EmitTargetCodeForMemcmp(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain,
SDValue Op1, SDValue Op2, SDValue Op3,
const CallInst *CI) const;
};

} // namespace llvm
Expand Down
3 changes: 1 addition & 2 deletions llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp
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Expand Up @@ -181,8 +181,7 @@ static SDValue addIPMSequence(const SDLoc &DL, SDValue CCReg,

std::pair<SDValue, SDValue> SystemZSelectionDAGInfo::EmitTargetCodeForMemcmp(
SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src1,
SDValue Src2, SDValue Size, MachinePointerInfo Op1PtrInfo,
MachinePointerInfo Op2PtrInfo) const {
SDValue Src2, SDValue Size, const CallInst *CI) const {
SDValue CCReg;
// Swap operands to invert CC == 1 vs. CC == 2 cases.
if (auto *CSize = dyn_cast<ConstantSDNode>(Size)) {
Expand Down
3 changes: 1 addition & 2 deletions llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.h
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Expand Up @@ -41,8 +41,7 @@ class SystemZSelectionDAGInfo : public SelectionDAGTargetInfo {
std::pair<SDValue, SDValue>
EmitTargetCodeForMemcmp(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain,
SDValue Src1, SDValue Src2, SDValue Size,
MachinePointerInfo Op1PtrInfo,
MachinePointerInfo Op2PtrInfo) const override;
const CallInst *CI) const override;

std::pair<SDValue, SDValue>
EmitTargetCodeForMemchr(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain,
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/PowerPC/memintr32.ll
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Expand Up @@ -11,7 +11,7 @@ define i32 @memcmp_test(ptr nocapture noundef readonly %ptr1, ptr nocapture noun
; CHECK-AIX-32-P9-NEXT: mflr r0
; CHECK-AIX-32-P9-NEXT: stwu r1, -64(r1)
; CHECK-AIX-32-P9-NEXT: stw r0, 72(r1)
; CHECK-AIX-32-P9-NEXT: bl .memcmp[PR]
; CHECK-AIX-32-P9-NEXT: bl .___memcmp[PR]
; CHECK-AIX-32-P9-NEXT: nop
; CHECK-AIX-32-P9-NEXT: addi r1, r1, 64
; CHECK-AIX-32-P9-NEXT: lwz r0, 8(r1)
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/PowerPC/memintr64.ll
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Expand Up @@ -39,7 +39,7 @@ define noundef i32 @_Z11memcmp_testPKvS0_m(ptr noundef readonly captures(none) %
; CHECK-AIX-64-P9-NEXT: mflr r0
; CHECK-AIX-64-P9-NEXT: stdu r1, -112(r1)
; CHECK-AIX-64-P9-NEXT: std r0, 128(r1)
; CHECK-AIX-64-P9-NEXT: bl .memcmp[PR]
; CHECK-AIX-64-P9-NEXT: bl .___memcmp64[PR]
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This doesn't look like a tail call? Make sure both tail and non-tail cases are tested?

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@diggerlin diggerlin Jul 10, 2025 •
edited
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This doesn't look like a tail call? Make sure both tail and non-tail cases are tested?

you are correct, the IR in the test case is tail call, but in AIX, it is not tail callable when using a toc - the reason being you have to do a toc restore after returning from the definition of memcmp since it lives in another library and the call sequence modifies r2 to point to the defining modules toc.

; CHECK-AIX-64-P9-NEXT: nop
; CHECK-AIX-64-P9-NEXT: addi r1, r1, 112
; CHECK-AIX-64-P9-NEXT: ld r0, 16(r1)
Expand Down