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[RISCV] Swap source register operands in QC_SHLADD ISEL patterns #149697

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Merged
merged 1 commit into from
Jul 21, 2025
Merged

[RISCV] Swap source register operands in QC_SHLADD ISEL patterns #149697

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4 changes: 2 additions & 2 deletions llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1377,9 +1377,9 @@ let Predicates = [HasVendorXqciac, IsRV32] in {
def : Pat<(i32 (add GPRNoX0:$rd, (mul GPRNoX0:$rs1, simm12:$imm12))),
(QC_MULIADD GPRNoX0:$rd, GPRNoX0:$rs1, simm12:$imm12)>;
def : Pat<(i32 (add_like_non_imm12 (shl GPRNoX0:$rs1, uimm5gt3:$imm), GPRNoX0:$rs2)),
(QC_SHLADD GPRNoX0:$rs2, GPRNoX0:$rs1, uimm5gt3:$imm)>;
(QC_SHLADD GPRNoX0:$rs1, GPRNoX0:$rs2, uimm5gt3:$imm)>;
def : Pat<(i32 (riscv_shl_add GPRNoX0:$rs1, uimm5gt3:$imm, GPRNoX0:$rs2)),
(QC_SHLADD GPRNoX0:$rs2, GPRNoX0:$rs1, uimm5gt3:$imm)>;
(QC_SHLADD GPRNoX0:$rs1, GPRNoX0:$rs2, uimm5gt3:$imm)>;
} // Predicates = [HasVendorXqciac, IsRV32]

/// Simple arithmetic operations
Expand Down
38 changes: 19 additions & 19 deletions llvm/test/CodeGen/RISCV/xqciac.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -231,12 +231,12 @@ define dso_local i32 @pow2(i32 %a, i32 %b) local_unnamed_addr #0 {
;
; RV32IMXQCIAC-LABEL: pow2:
; RV32IMXQCIAC: # %bb.0: # %entry
; RV32IMXQCIAC-NEXT: qc.shladd a0, a0, a1, 5
; RV32IMXQCIAC-NEXT: qc.shladd a0, a1, a0, 5
; RV32IMXQCIAC-NEXT: ret
;
; RV32IZBAMXQCIAC-LABEL: pow2:
; RV32IZBAMXQCIAC: # %bb.0: # %entry
; RV32IZBAMXQCIAC-NEXT: qc.shladd a0, a0, a1, 5
; RV32IZBAMXQCIAC-NEXT: qc.shladd a0, a1, a0, 5
; RV32IZBAMXQCIAC-NEXT: ret
entry:
%mul = mul nsw i32 %b, 32
Expand Down Expand Up @@ -276,12 +276,12 @@ define dso_local i32 @shladd(i32 %a, i32 %b) local_unnamed_addr #0 {
;
; RV32IMXQCIAC-LABEL: shladd:
; RV32IMXQCIAC: # %bb.0: # %entry
; RV32IMXQCIAC-NEXT: qc.shladd a0, a0, a1, 31
; RV32IMXQCIAC-NEXT: qc.shladd a0, a1, a0, 31
; RV32IMXQCIAC-NEXT: ret
;
; RV32IZBAMXQCIAC-LABEL: shladd:
; RV32IZBAMXQCIAC: # %bb.0: # %entry
; RV32IZBAMXQCIAC-NEXT: qc.shladd a0, a0, a1, 31
; RV32IZBAMXQCIAC-NEXT: qc.shladd a0, a1, a0, 31
; RV32IZBAMXQCIAC-NEXT: ret
entry:
%shl = shl nsw i32 %b, 31
Expand All @@ -305,9 +305,9 @@ define dso_local i64 @shladd64(i64 %a, i64 %b) local_unnamed_addr #0 {
; RV32IMXQCIAC-LABEL: shladd64:
; RV32IMXQCIAC: # %bb.0: # %entry
; RV32IMXQCIAC-NEXT: srli a4, a2, 1
; RV32IMXQCIAC-NEXT: qc.shladd a0, a0, a2, 31
; RV32IMXQCIAC-NEXT: qc.shladd a0, a2, a0, 31
; RV32IMXQCIAC-NEXT: slli a2, a2, 31
; RV32IMXQCIAC-NEXT: qc.shladd a3, a4, a3, 31
; RV32IMXQCIAC-NEXT: qc.shladd a3, a3, a4, 31
; RV32IMXQCIAC-NEXT: sltu a2, a0, a2
; RV32IMXQCIAC-NEXT: add a1, a1, a3
; RV32IMXQCIAC-NEXT: add a1, a1, a2
Expand All @@ -316,9 +316,9 @@ define dso_local i64 @shladd64(i64 %a, i64 %b) local_unnamed_addr #0 {
; RV32IZBAMXQCIAC-LABEL: shladd64:
; RV32IZBAMXQCIAC: # %bb.0: # %entry
; RV32IZBAMXQCIAC-NEXT: srli a4, a2, 1
; RV32IZBAMXQCIAC-NEXT: qc.shladd a0, a0, a2, 31
; RV32IZBAMXQCIAC-NEXT: qc.shladd a0, a2, a0, 31
; RV32IZBAMXQCIAC-NEXT: slli a2, a2, 31
; RV32IZBAMXQCIAC-NEXT: qc.shladd a3, a4, a3, 31
; RV32IZBAMXQCIAC-NEXT: qc.shladd a3, a3, a4, 31
; RV32IZBAMXQCIAC-NEXT: sltu a2, a0, a2
; RV32IZBAMXQCIAC-NEXT: add a1, a1, a3
; RV32IZBAMXQCIAC-NEXT: add a1, a1, a2
Expand All @@ -338,12 +338,12 @@ define dso_local i32 @shladd_ordisjoint(i32 %a, i32 %b) local_unnamed_addr #0 {
;
; RV32IMXQCIAC-LABEL: shladd_ordisjoint:
; RV32IMXQCIAC: # %bb.0: # %entry
; RV32IMXQCIAC-NEXT: qc.shladd a0, a0, a1, 22
; RV32IMXQCIAC-NEXT: qc.shladd a0, a1, a0, 22
; RV32IMXQCIAC-NEXT: ret
;
; RV32IZBAMXQCIAC-LABEL: shladd_ordisjoint:
; RV32IZBAMXQCIAC: # %bb.0: # %entry
; RV32IZBAMXQCIAC-NEXT: qc.shladd a0, a0, a1, 22
; RV32IZBAMXQCIAC-NEXT: qc.shladd a0, a1, a0, 22
; RV32IZBAMXQCIAC-NEXT: ret
entry:
%shl = shl nsw i32 %b, 22
Expand All @@ -361,13 +361,13 @@ define dso_local i32 @shladdc1c2(i32 %a, i32 %b) local_unnamed_addr #0 {
;
; RV32IMXQCIAC-LABEL: shladdc1c2:
; RV32IMXQCIAC: # %bb.0: # %entry
; RV32IMXQCIAC-NEXT: qc.shladd a0, a1, a0, 5
; RV32IMXQCIAC-NEXT: qc.shladd a0, a0, a1, 5
; RV32IMXQCIAC-NEXT: slli a0, a0, 26
; RV32IMXQCIAC-NEXT: ret
;
; RV32IZBAMXQCIAC-LABEL: shladdc1c2:
; RV32IZBAMXQCIAC: # %bb.0: # %entry
; RV32IZBAMXQCIAC-NEXT: qc.shladd a0, a1, a0, 5
; RV32IZBAMXQCIAC-NEXT: qc.shladd a0, a0, a1, 5
; RV32IZBAMXQCIAC-NEXT: slli a0, a0, 26
; RV32IZBAMXQCIAC-NEXT: ret
entry:
Expand All @@ -388,7 +388,7 @@ define dso_local i32 @shxaddc1c2(i32 %a, i32 %b) local_unnamed_addr #0 {
; RV32IMXQCIAC-LABEL: shxaddc1c2:
; RV32IMXQCIAC: # %bb.0: # %entry
; RV32IMXQCIAC-NEXT: slli a1, a1, 28
; RV32IMXQCIAC-NEXT: qc.shladd a0, a1, a0, 31
; RV32IMXQCIAC-NEXT: qc.shladd a0, a0, a1, 31
; RV32IMXQCIAC-NEXT: ret
;
; RV32IZBAMXQCIAC-LABEL: shxaddc1c2:
Expand Down Expand Up @@ -417,18 +417,18 @@ define dso_local i64 @shladdc1c264(i64 %a, i64 %b) local_unnamed_addr #0 {
; RV32IMXQCIAC-LABEL: shladdc1c264:
; RV32IMXQCIAC: # %bb.0: # %entry
; RV32IMXQCIAC-NEXT: srli a1, a2, 12
; RV32IMXQCIAC-NEXT: qc.shladd a1, a1, a3, 20
; RV32IMXQCIAC-NEXT: qc.shladd a1, a3, a1, 20
; RV32IMXQCIAC-NEXT: slli a2, a2, 20
; RV32IMXQCIAC-NEXT: qc.shladd a1, a1, a0, 23
; RV32IMXQCIAC-NEXT: qc.shladd a1, a0, a1, 23
; RV32IMXQCIAC-NEXT: mv a0, a2
; RV32IMXQCIAC-NEXT: ret
;
; RV32IZBAMXQCIAC-LABEL: shladdc1c264:
; RV32IZBAMXQCIAC: # %bb.0: # %entry
; RV32IZBAMXQCIAC-NEXT: srli a1, a2, 12
; RV32IZBAMXQCIAC-NEXT: qc.shladd a1, a1, a3, 20
; RV32IZBAMXQCIAC-NEXT: qc.shladd a1, a3, a1, 20
; RV32IZBAMXQCIAC-NEXT: slli a2, a2, 20
; RV32IZBAMXQCIAC-NEXT: qc.shladd a1, a1, a0, 23
; RV32IZBAMXQCIAC-NEXT: qc.shladd a1, a0, a1, 23
; RV32IZBAMXQCIAC-NEXT: mv a0, a2
; RV32IZBAMXQCIAC-NEXT: ret
entry:
Expand All @@ -449,13 +449,13 @@ define dso_local i32 @shladdc1equalc2(i32 %a, i32 %b) local_unnamed_addr #0 {
; RV32IMXQCIAC-LABEL: shladdc1equalc2:
; RV32IMXQCIAC: # %bb.0: # %entry
; RV32IMXQCIAC-NEXT: slli a1, a1, 12
; RV32IMXQCIAC-NEXT: qc.shladd a0, a1, a0, 12
; RV32IMXQCIAC-NEXT: qc.shladd a0, a0, a1, 12
; RV32IMXQCIAC-NEXT: ret
;
; RV32IZBAMXQCIAC-LABEL: shladdc1equalc2:
; RV32IZBAMXQCIAC: # %bb.0: # %entry
; RV32IZBAMXQCIAC-NEXT: slli a1, a1, 12
; RV32IZBAMXQCIAC-NEXT: qc.shladd a0, a1, a0, 12
; RV32IZBAMXQCIAC-NEXT: qc.shladd a0, a0, a1, 12
; RV32IZBAMXQCIAC-NEXT: ret
entry:
%shlc1 = shl nsw i32 %a, 12
Expand Down
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