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A-LLVMArea: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues.Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues.O-riscvTarget: RISC-V architectureTarget: RISC-V architectureT-compilerRelevant to the compiler team, which will review and decide on the PR/issue.Relevant to the compiler team, which will review and decide on the PR/issue.
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#52787 added support only for riscv32imac_unknown_none_elf.
I am working on riscv64imac_unknown_none_elf soft cores (running sel4) and would love to be able to use Rust, in particular: https://github.com/PolySync/cargo-fel4
I don't know the domain yet but would love to learn by going through the PR submission process to add that architecture if there are no reasons to exclude it. Are there reasons for not including riscv64imac related to hardware in the wild?
/cc @japaric
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A-LLVMArea: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues.Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues.O-riscvTarget: RISC-V architectureTarget: RISC-V architectureT-compilerRelevant to the compiler team, which will review and decide on the PR/issue.Relevant to the compiler team, which will review and decide on the PR/issue.